A) Brevets

1. D. Audet and L. Parent, “System for on-line measurement of electrical conductivity of crude anode for aluminum production”, Brevet américain no 7576534, 2009.

2. L. Parent and D. Audet, « System and method for measuring liquid metal levels or the like, » Brevet américain no 6577118, 2003

B) Articles parus dans des revues avec comité de lecture

1. Y.S. Kocaefe, G. Simard, D. Audet, and J. Beaulieu, « Application of Parallel Computing to the Hybrid Zone-Monte Carlo Method Using PVM, » Advanced Concepts an Techniques in Thermal Modelling, D. Lemonnier et al. editors, Elsevier, Paris, pp. 346-352, 1996.

2. D. Audet and Y. Savaria, « High-Speed Interconnections Using True Single-Phase Clocking, » Journal of Microelectronic Systems Integration, vol. 3, no. 4, pp. 247-257, Dec. 1995.

3. R. Kermouche, D. Audet and Y. Savaria, « On the Optimization of Integrated Hierarchical Bus Architectures to Achieve Efficient Fault-Tolerance, » Journal of Microelectronic Systems Integration, vol. 3, no. 1, pp. 47-64, Mar. 1995.

4. D. Audet and Y. Savaria, « An Architectural Approach for Increasing Clock Frequency and Communication Speed in Monolithic WSI Systems, » IEEE Trans. on Components, Packaging and Manufacturing Technology, part B, vol. 17, no. 3, pp. 362-368, Aug. 1994.

5. D. Audet, Y. Savaria, and N. Arel, « Pipelining Communications in VLSI/ULSI Systems, » IEEE Trans. on VLSI Systems, vol. 2, no. 1, pp. 1-10, March 1994.

6. D. Audet, Y. Savaria, and J.L. Houle, « Performance Improvement to VLSI Parallel Systems, Using Dynamic Concatenation of Processing Resources, » Parallel Computing, Elsevier/North-Holland, 18, pp. 149-167, 1992.

C) Articles parus dans des comptes rendus de conférences

1. D. Audet, L. Parent, M. Deveaux, and J. Courtenay, « Aluminum Weighing Measurement in Tilting Furnaces », 133rd TMS Annual Meting, Carlotte NC, 2004.

2. L. Thériault, D. Audet, and Y. Savaria, « Performance estimators for Hardware/Software Co-design, » Proc. IEEE International Symposium on Circuits and Systems, » Sydney, Australia, May 6-9, 2001.

3. D. Audet, S. Masson, and Y. Savaria, « Reducing Fault Sensitivity of Microprocessor-Based System by Modifying Workload Structure, » Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (USA), November 2-4, 1998, pp. 241-249.

4. D. Audet, N. Gagnon, and Y. Savaria, « Implementing Fault-Injection and Tolerance Mechanisms in Multiprocessor Systems, » IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Boston (USA), November 6-8, 1996, pp.310-317.

5. D. Audet, N. Gagnon, and Y. Savaria, « Quantitative Comparisons of TMR Implementations in a Multiprocessor System, » IEEE International On-Line Testing Workshop, Biarritz (France), July 1996, pp. 196-199.

6. D. Audet and Y. Savaria, « High-Speed Interconnections Using True Single-Phase Clocking, » Proc. of the IEEE International Conf. on Wafer Scale Integration, San Francisco, Jan. 1995, pp. 258-265.

7. 5.J. Rouat, F. He, and D. Audet, « A Neural Network for Speech Encryption and Filtering, » Proc. of World Congress on Neural Network, San Diego, June 1994, vol. IV, pp. 620-625.

8. Y.S. Kocaefe, G. Simard, D. Audet, and J. Beaulieu, « Application of Parallel Computing to the Hybrid Zone-Monte Carlo Method Using PVM, » Proc. of Eurotherm, Poitiers (France), Sept. 1994, pp. R16-R23.

9. D. Audet and Y. Savaria, « An Architectural Approach for Increasing Clock Frequency and Communication Speed in Monolithic WSI Systems (short version), » Proc. IEEE International Conf. on Wafer Scale Integration, San Francisco, Jan. 1994, pp. 235-243.

10. R. Kermouche, Y. Savaria, and D. Audet, « Harvest Model of an Integrated Hierarchical- Bus Architecture, » Proc. IEEE International Conf. on Wafer Scale Integration, San Francisco, Jan. 1994, pp. 69-78.

11. E. Chabot and D. Audet, « Estimating Optimum Parallelism in Standard Scientific Applications, » Proc. 6th SIAM Conf. on Parallel Processing for Scientific Computing, Norfolk VA, March 1993, pp. 1015-1018.

12. T.V. Ho, D. Audet, and Y. Savaria, « Performance Models for Optimizing a Hierarchical- Bus Multiprocessor Architecture, » Proc. Canadian Conf. On Electrical and Comput. Eng., Vancouver, Sept. 1993, pp. 361-364.

13. D. Audet, J.L. Houle, and Y. Savaria, « A Dynamic Concatenation Approach to Enhance Parallel Processing, » Proc. Canadian Conf. on Electrical and Comput. Eng., Montreal, Sept. 1989, pp. 851-854.

14. D. Audet, C. Cyr, J.L. Houle, and Y. Savaria, « IMAGE2 – A Flexible Multiprocessor Chip for Image Processing, » Proc. International Symposium on Mini and Microcomputers, Miami Beach, Dec. 1988, pp. 136-139.

15. C. Cyr, Y. Savaria, D. Audet, and J.L. Houle, « A Novel Self-Testing and Reconfiguration Scheme for Yield Improvement of Two Dimensional Logic Arrays, » Proc IEEE Int. Conf. on Computer Design: VLSI in Computers, Oct. 1987, pp. 494-500.

16. D. Audet, J.L. Houle, and C. Cyr, « An Instruction Set for IMAGE2, a VLSI Systolic Processor, » Proc. Canadian Conf on VLSI, Winnipeg, Oct. 1987, pp. 313-318

17. D. Audet, J.L. Houle, and Y. Savaria, « Functional Simulation of VLSI Reconfigurable Processors, » Proc. Summer Conf. on Simulation, Aug. 1987, pp. 79-83.

18. D. Audet, J.L. Houle, and Y. Savaria, « Algorithms and VLSI Architectures for Parallel Processing of Images, » Platinum Jubilee Conference on Systems and Signal Processing, Bengalore, Dec. 1986, pp. 313-316.

19. C. Cyr, D. Audet, Y. Savaria, and J.L. Houle, « IMAGE1 – A VLSI Cell for Systolic Image Processing, » Proc. Canadian Conf. on VLSI, Montreal, Oct. 1986, pp. 375-380.

D) Publications gouvernementales (rapports au ministère de la défense nationale)

1. D. Audet, Y. Savaria, N. Gagnon and D. Ouellet, « Final Report on Further Anomalous Behavior of Hardware Prototypes, » Contract Report (W2207-4-AF06/2), Sept. 1998, 43 pages.

2. D. Audet, Y. Savaria, N. Gagnon and D. Ouellet, « Report on Further Anomalous Behavior of Hardware Prototypes, » Contract Report (W2207-4-AF06), Mar. 1997, 23 pages.

3. Y. Savaria, D. Audet, and N. Arel, « Final Report, » Contract Report (W2207-0-AF14/01- SS), Apr. 1994, 52 pages.

4. N. Arel, D. Audet, and Y. Savaria, « Functional Simulator and Executable Models – Version 2, » Contract Report (W2207-0-
AF14/01-SS), Apr. 1994, 127 pages.

5. D. Audet, Y. Savaria, and N. Arel, « Report on the Routers Tests, » Contract Report (W2207-0-AF14/01-SS), Apr. 1994, 9 pages.

6. Y. Savaria, D. Audet, and N. Arel, « State-of-the-art in Large Area Integration and Scalability to ULSI, » Contract Report (W2207-0-AF14/01-SS), Dec. 1993, 93 pages.

7. Y. Savaria, D. Audet, and N. Arel, « Fault-Injection and Restructuring in the HiBus Prototype, » Contract Report (W2207-0-
AF14/01-SS), Nov. 1993, 33 pages.

8. D. Audet, Y. Savaria, and N. Arel, « FATMOS – A Fault-Tolerant Multiprocessor Operating System, » Contract Report (W2207-0-AF14/01-SS), Nov. 1993, 33 pages.

9. D. Audet, Y. Savaria, and N. Arel, « The Repeater: Functional Description and Implementation, » Contract Report (W2207-
0-AF14/01-SS), Apr. 1992, 39 pages.

10. Y. Savaria, D. Audet, and N. Arel, « The Routers: From a Functional to a Detailed Implementation Description, » Contract
Report (W2207-0-AF14/01-SS), Jan. 1992, 39 pages.

11. N. Arel, D. Audet, and Y. Savaria, « Report on a Functional Simulator for the Proposed ULSI Architecture, » Contract
Report (W2207-0-AF14/01-SS), Sept. 1991, 44 pages.

12. D. Audet, Y. Savaria, and N. Arel, « Feasibility Assessment of Self-Timed Communications in the Proposed ULSI Architecture, » Contract Report (W2207-0- AF14/01-SS), July 1991, 47 pages.

13. Y. Savaria, D. Audet, and N. Arel, « Methods of On-Line Error Dectection and Correction in ULSI Architectures, » Contract
Report (W2207-0-AF14/01-SS), Jun. 1991, 70 pages.